rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7541a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 cmos 12-bit monolithic multiplying dac functional block diagram 10k w 10k w 10k w 20k w 20k w 20k w 20k w 20k w s1 s2 s3 s12 v ref out2 out1 r feedback bit 12 (lsb) bit 3 bit 2 bit 1 (msb) digital inputs (dtl/ttl/cmos compatible) logic: a switch is closed to i out1 for its digital input in a "high" state. 10k w features improved version of ad7541 full four-quadrant multiplication 12-bit linearity (endpoint) all parts guaranteed monotonic ttl/cmos compatible low cost protection schottky diodes not required low logic input leakage general description the analog devices ad7541a is a low cost, high performance 12-bit monolithic multiplying digital-to-analog converter. it is fabricated using advanced, low noise, thin film on cmos technology and is available in a standard 18-lead dip and in 20-terminal surface mount packages. the ad7541a is functionally and pin compatible with the in- dustry standard ad7541 device and offers improved specifica- tions and performance. the improved design ensures that the device is latch-up free so no output protection schottky diodes are required. this new device uses laser wafer trimming to provide full 12-bit endpoint linearity with several new high performance grades. product highlights compatibility: the ad7541a can be used as a direct replace- ment for any ad7541-type device. as with the analog devices ad7541, the digital inputs are ttl/cmos compatible and have been designed to have a 1 m a maximum input current requirement so as not to load the driving circuitry. improvements: the ad7541a offers the following improved specifications over the ad7541: 1. gain error for all grades has been reduced with premium grade versions having a maximum gain error of 3 lsb. 2. gain error temperature coefficient has been reduced to 2 ppm/ c typical and 5 ppm/ c maximum. 3. digital-to-analog charge injection energy for this new device is typically 20% less than the standard ad7541 part. 4. latch-up proof. 5. improvements in laser wafer trimming provides 1/2 lsb max differential nonlinearity for top grade devices over the operat- ing temperature range (vs. 1 lsb on older 7541 types). 6. all grades are guaranteed monotonic to 12 bits over the operating temperature range. ordering guide 1 relative gain temperature accuracy error package model 2 range t min to t max t a = +25 8 c options 3 ad7541ajn 0 c to +70 c 1 lsb 6 lsb n-18 ad7541akn 0 c to +70 c 1/2 lsb 1 lsb n-18 AD7541AJP 0 c to +70 c 1 lsb 6 p-20a ad7541akp 0 c to +70 c 1/2 lsb 1 p-20a ad7541akr 0 c to +70 c 1/2 lsb 1 r-18 ad7541aaq C25 c to +85 c 1 lsb 6 lsb q-18 ad7541abq C25 c to +85 c 1/2 lsb 1 lsb q-18 ad7541asq C55 c to +125 c 1 lsb 6 lsb q-18 ad7541atq C55 c to +125 c 1/2 lsb 1 lsb q-18 ad7541ase C55 c to +125 c 1 lsb 6 lsb e-20a ad7541ate C55 c to +125 c 1/2 lsb 1 lsb e-20a notes 1 analog devices reserves the right to ship either ceramic (d-18) or cerdip (q-18) hermetic packages. 2 to order mil-std-883, class b process parts, add /883b to part number. contact local sales office for military data sheet. 3 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = small outline ic.
C2C rev. b ad7541aCspecifications t a =t a = parameter version +25 8 ct min, t max 1 units test conditions/comments accuracy resolution all 12 12 bits relative accuracy j, a, s 1 1 lsb max 1 lsb = 0.024% of full scale k, b, t 1/2 1/2 lsb max 1/2 lsb = 0.012% of full scale differential nonlinearity j, a, s 1 1 lsb max all grades guaranteed monotonic k, b, t 1/2 1/2 lsb max to 12 bits, t min to t max . gain error j, a, s 6 8 lsb max measured using internal r fb and includes k, b, t 3 5 lsb max effect of leakage current and gain tc. gain error can be trimmed to zero. gain temperature coefficient 2 d gain/ d temperature all 5 5 ppm/ c max typical value is 2 ppm/ c. output leakage current out1 (pin 1) j, k 5 10 na max all digital inputs = 0 v. a, b 5 10 na max s, t 5 200 na max out2 (pin 2) j, k 5 10 na max all digital inputs = v dd . a, b 5 10 na max s, t 5 200 na max reference input input resistance (pin 17 to gnd) all 7C18 7C18 k w min/max typical input resistance = 11 k w . typical input resistance temperature coefficient = C300 ppm/ c. digital inputs v ih (input high voltage) all 2.4 2.4 v min v il (input low voltage) all 0.8 0.8 v max i in (input current) all 1 1 m a max logic inputs are mos gates. i in typ (25 c) = 1 na. c in (input capacitance) 2 all 8 8 pf max v in = 0 v power supply rejection d gain/ d v dd all 0.01 0.02 % per % max d v dd = 5% power supply v dd range all +5 to +16 +5 to +16 v min/v max accuracy is not guaranteed over this range. i dd all 2 2 ma max all digital inputs v il or v ih . 100 500 m a max all digital inputs 0 v or v dd . ac performance characteristics these characteristics are included for design guidance only and are not subject to test. v dd = +15 v, v in = +10 v except where noted, out1 = 0ut2 = gnd = 0 v, output amp is ad544 except where noted. t a =t a = parameter version 1 +25 8 ct min, t max 1 units test conditions/comments propagation delay (from digital input out 1 load = 100 w , c ext = 13 pf. change to 90% of final analog output) all 100 ns typ digital inputs = 0 v to v dd or v dd to 0 v. digital to analog glitch v ref = 0 v. all digital inputs 0 v to v dd or impulse v dd to 0 v. all 1000 nv-sec typ measured using model 50k as output amplifier. multiplying feedthrough error 3 (v ref to out1) all 1.0 mv p-p typ v ref = 10 v, 10 khz sine wave. output current settling time all 0.6 m s typ to 0.01% of full-scale range. out 1 load = 100 w , c ext = 13 pf. digital inputs = 0 v to v dd or v dd to 0 v. output capacitance c out1 (pin 1) all 200 200 pf max digital inputs c out2 (pin 2) all 70 70 pf max = v ih c out1 (pin 1) all 70 70 pf max digital inputs c out2 (pin 2) all 200 200 pf max = v il notes 1 temperature range as follows: j, k versions, 0 c to +70 c; a, b versions, C25 c to +85 c; s, t versions, C55 c to +125 c. 2 guaranteed by design but not production tested. 3 to minimize feedthrough in the ceramic package (suffix d) the user must ground the metal lid. specifications subject to change without notice. (v dd = +15 v, v ref = +10 v; out 1 = out 2 = gnd = 0 v unless otherwise noted)
ad7541a C3C rev. b absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v digital input voltage to gnd . . . . . . . . C0.3 v, v dd + 0.3 v out 1, out 2 to gnd . . . . . . . . . . . . C0.3 v, v dd + 0.3 v power dissipation (any package) to +75 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mw derates above +75 c . . . . . . . . . . . . . . . . . . . . . . 6 mw/ c terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is expressed in % of full- scale range or (sub)multiples of 1 lsb. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal l lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range insures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output. for the ad7541a, ideal maximum output is C 4095 4096 ? ? ? ? ( v ref ). gain error is adjustable to zero using external trims as shown in figures 4, 5 and 6. output leakage current current which appears at outi with the dac loaded to all 0s or at out2 with the dac loaded to all 1s. multiplying feedthrough error ac error due to capacitive feedthrough from v ref terminal to out1 with dac loaded to all 0s. output current settling time time required for the output function of the dac to settle to within 1/2 lsb for a given digital input stimulus, i.e., 0 to full scale. propagation delay this is a measure of the internal delay of the circuit and is mea- sured from the time a digital input changes to the point at which the analog output at out1 reaches 90% of its final value. digital-to-analog charge injection (qda) this is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. it is usually specified as the area of the glitch in nv secs and is measured with v ref = gnd and a model 50k as the output op amp, c1 (phase compensation) = 0 pf. operating temperature range commercial (j, k versions) . . . . . . . . . . . . . 0 c to +70 c industrial (a, b versions) . . . . . . . . . . . . . C25 c to +85 c extended (s, t versions) . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7541a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations dip/soic lccc plcc 14 13 12 11 17 16 15 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad7541a out1 bit 12 (lsb) v dd (+) v ref in r feedback out2 gnd bit 1 (msb) bit 9 bit 10 bit 11 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 20 19 1 2 3 out 2 out 1 nc r fb v ref bit 5 bit 6 18 14 15 16 17 4 5 6 7 8 9 10111213 top view (not to scale) ad7541a gnd bit 1 (msb) bit 2 bit 3 bit 4 v dd bit 12 (lsb) bit 11 bit 10 bit 9 nc = no connect nc bit 7 bit 8 20 19 18 1 2 3 4 5 6 7 8 9101112 13 14 15 16 17 top view (not to scale) pin 1 identifier gnd bit 1 (msb) bit 2 bit 3 bit 4 v dd bit 12 (lsb) bit 11 bit 10 bit 9 nc = no connect out 2 out 1 nc r fb v ref ad7541a bit 5 bit 6 nc bit 7 bit 8
ad7541a C4C rev. b general circuit information the simplified d/a circuit is shown in figure 1. an inverted r-2r ladder structure is usedthat is, the binarily weighted currents are switched between the out1 and out2 bus lines, thus maintaining a constant current in each ladder leg indepen- dent of the switch state. 10k w 10k w 10k w 20k w 20k w 20k w 20k w 20k w s1 s2 s3 s12 v ref out2 out1 r feedback bit 12 (lsb) bit 3 bit 2 bit 1 (msb) digital inputs (dtl/ttl/cmos compatible) logic: a switch is closed to i out1 for its digital input in a "high" state. 10k w figure 1. functional diagram (inputs high) the input resistance at v ref (figure 1) is always equal to r ldr (r ldr is the r/2r ladder characteristic resistance and is equal to value r). since r in at the v ref pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (if a current source is used, a low temperature coefficient external r fb is recommended to define scale factor.) equivalent circuit analysis the equivalent circuits for all digital inputs low and all digital inputs high are shown in figures 2 and 3. in figure 2 with all digital inputs low, the reference current is switched to out2. the current source i leakage is composed of surface and junc- tion leakages to the substrate, while the i/ 4096 current source represents a constant 1-bit current drain through the termina- tion resistor on the r-2r ladder. the on capacitance of the output n-channel switch is 200 pf, as shown on the out2 terminal. the off switch capacitance is 70 pf, as shown on the out1 terminal. analysis of the circuit for all digital inputs high, as shown in figure 3 is similar to figure 2; however, the on switches are now on terminal out1, hence the 200 pf at that terminal. i leakage 70pf r i leakage 200pf i /4096 i ref r 15k w v ref rfb out1 out2 figure 2. dac equivalent circuit all digital inputs low i leakage 70pf r i leakage 200pf i /4096 i ref r 15k w v ref rfb out2 out1 figure 3. dac equivalent circuit all digital inputs high applications unipolar binary operation (2-quadrant multiplication) figure 4 shows the analog circuit connections required for uni- polar binary (2-quadrant multiplication) operation. with a dc reference voltage or current (positive or negative polarity) ap- plied at pin 17, the circuit is a unipolar d/a converter. with an ac reference voltage or current, the circuit provides 2-quadrant multiplication (digitally controlled attenuation). the input/ output relationship is shown in table ii. r1 provides full-scale trim c apability [i.e., load the dac register to 1111 1111 1111, adjust r1 for v out = Cv ref (4095/4096)]. alternatively, full scale can be adjusted by omitting r1 and r2 and trimming the reference voltage magnitude. c1 phase compensation (10 pf to 25 pf) may be required for stability when using high speed amplifiers. (c1 is used to cancel the pole formed by the dac internal feedback resistance and output capacitance at out1). amplifier a1 should be selected or trimmed to provide v os 10% of the voltage resolution at v out . additionally, the ampli- fier should exhibit a bias current which is low over the tempera- ture range of interest (bias current causes output offset at v out equal to i b times the dac feedback resistance, nominally 11 k w ). the ad544l is a high speed implanted fet input op amp with low factory-trimmed v os . 18 16 1 2 3 17 ad7541a v dd r fb v dd v ref pins 4?5 dgnd out1 out2 r1 * v in bit 1 ?bit 12 digital ground analog common r2 * c1 33pf ad544l (see text) v out * refer to table 1 figure 4. unipolar binary operation table i. recommended trim resistor values vs. grades trim resistor jn/aq/sd kn/bq/td r1 100 w 100 w r2 47 w 33 w table ii. unipolar binary code table for circuit of figure 4 binary number in dac msb lsb analog output, v out 1 1 1 1 1 1 1 1 1 1 1 1 Cv in 4095 4096 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 Cv in 2048 4096 ? ? ? ? = C1/2 v in 0 0 0 0 0 0 0 0 0 0 0 1 Cv in 1 4096 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 volts
ad7541a C5C rev. b bipolar operation (4-quadrant multiplication) figure 5 and table iii illustrate the circuitry and code relation- ship for bipolar operation. with a dc reference (positive or nega- tive polarity) the circuit provides offset binary operation. with an ac reference the circuit provides full 4-quadrant multiplication. with the dac loaded to 1000 0000 0000, adjust r1 for v out = 0 v (alternatively, one can omit r1 and r2 and adjust the ratio of r3 to r4 for v out = 0 v). full-scale trimming can be accomplished by adjusting the amplitude of v ref or by vary- ing the value of r5. as in unipolar operation, a1 must be chosen for low v os and low i b . r3, r4 and r5 must be selected for matching and track- ing. mismatch of 2r3 to r4 causes both offset and full-scale error. mismatch of r5 to r4 or 2r3 causes full-scale error. c1 phase compensation (10 pf to 50 pf) may be required for sta- bility, depending on amplifier used. ad7541a a1 3 r2 * v dd 16 17 18 1 2 v dd r fb v ref pins 4?5 gnd out1 out2 r1 * v in bit 1 ?bit 12 digital ground analog common c1 33pf ad544l v out ad544j a2 r4 20k w r5 20k w r3 10k w r6 5k w 10% * for values of r1 and r2 see table 1. figure 5. bipolar operation (4-quadrant multiplication) table iii. bipolar code table for offset binary circuit of figure 5 binary number in dac msb lsb analog output, v out 1 1 1 1 1 1 1 1 1 1 1 1 +v in 2047 2048 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 +v in 1 2048 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 0 volts 0 1 1 1 1 1 1 1 1 1 1 1 Cv in 1 2048 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 Cv in 2048 2048 ? ? ? ? figure 6 and table iv show an alternative method of achieving bipolar output. the circuit operates with sign plus magnitude code and has the advantage of giving 12-bit resolution in each quadrant, compared with 11-bit resolution per quadrant for the circuit of figure 5. the ad7592 is a fully protected cmos changeover switch with data latches. r4 and r5 should match each other to 0.01% to maintain the accuracy of the d/a con- verter. mismatch between r4 and r5 introduces a gain error. a2 ad7541a a1 3 r2 * v dd 16 17 18 1 2 v dd r fb v ref pins 4?5 gnd out1 out2 r1 * v in bit 1 ?bit 12 digital ground analog common c1 33pf ad544l v out ad544j r5 20k w * for values of r1 and r2 see table 1. r4 20k w r3 10k w 10% 1/2 ad7592jn sign bit figure 6. 12-bit plus sign magnitude operation table iv. 12-bit plus sign magnitude code table for circuit of figure 6 sign binary number in dac bit msb lsb analog output, v out 0 1 1 1 1 1 1 1 1 1 1 1 1 +v in 4095 4096 ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 volts 1 0 0 0 0 0 0 0 0 0 0 0 0 0 volts 1 1 1 1 1 1 1 1 1 1 1 1 1 Cv in 4095 4096 ? ? ? ? note: sign bit of 0 connects r3 to gnd.
ad7541a C6C rev. b applications hints output offset: cmos d/a converters exhibit a code-depen dent output resistance which in turn can cause a code-dependent error voltage at the output of the amplifier. the maximum am- plitude of this offset, which adds to the d/a converter nonlin- earity, is 0.67 v os where v os is the amplifier input offset voltage. to maintain monotonic operation it is recommended that v os be no greater than (25 10 C6 ) (v ref ) over the tempera- ture range of operation. suitable op amps are ad517l and ad544l. the ad517l is best suited for fixed reference appli- cations with low bandwidth requirements: it has extremely low offset (50 m v) and in most applications will not require an offset trim. the ad544l has a much wider bandwidth and higher slew rate and is recommended for multiplying and other appli- cations requiring fast settling. an offset trim on the ad544l may be necessary in some circuits. digital glitches: one cause of digital glitches is capacitive coupling from the digital lines to the out1 and out2 termi- nals. this should be minimized by screening the analog pins of the ad7541a (pins 1, 2, 17, 18) from the digital pins by a ground track run between pins 2 and 3 and between pins 16 and 17 of the ad7541a. note how the analog pins are at one end of the package and separated from the digital pins by v dd and gnd to aid screening at the board level. on-chip capacitive coupling can also give rise to crosstalk from the digital-to-analog sections of the ad7541a, particularly in circuits with high cur- rents and fast rise and fall times. temperature coefficients: the gain temperature coefficient of the ad7541a has a maximum value of 5 ppm/ c and a typi- cal value of 2 ppm/ c. this corresponds to worst case gain shifts of 2 lsbs and 0.8 lsbs, respectively, over a 100 c temperature range. when trim resistors r1 and r2 are used to adjust full- scale range, the temperature coefficient of r1 and r2 should also be taken into account. the reader is referred to analog devices application note gain error and gain temperature coefficient of cmos multiplying dacs, publication number e630c-5-3/86. single supply operation figure 7 shows the ad7541a connected in a voltage switching mode. out1 is connected to the reference voltage and out2 is connected to gnd. the d/a converter output voltage is available at the v ref pin (pin 17) and has a constant output impedance equal to r ldr . the feedback resistor r fb is not used in this circuit. 1 2 pins 4?5 ad7541a r fb v ref gnd out1 out2 bit 1 ?bit 12 16 18 17 3 not used v dd v out = 0v to +10v r2 30k w r1 10k w system ground v+ v ca3140b v dd = +15v v ref +2.5v v out v ref d (1 +r2/r1) where 0 d 1 i.e., d is a fractional representation of the digital input 15 4 figure 7. single supply operation using voltage switch- ing mode the reference voltage must always be positive. if out1 goes more than 0.3 v less than gnd, an internal diode will be turned on and a heavy current may flow causing device damage (the ad7541a is, however, protected from the scr latch-up phenomenon prevalent in many cmos devices). suitable refer- ences include the ad580 and ad584. the loading on the reference voltage source is code-dependent and the response time of the circuit is often determined by the behavior of the reference voltage with changing load conditions. to maintain linearity, the voltage at out1 should remain within 2.5 v of gnd, for a v dd of 15 v. if v dd is reduced from 15 v or the reference voltage at out1 increased to more than 2.5 v, the differential nonlinearity of the dac will increase and the linearity of the dac will be degraded. supplemental application material for further information on cmos multiplying d/a converters, the reader is referred to the following texts: cmos dac application guide, publication number g872b-8-1/89 available from analog devices. gain error and gain temperature coefficient of cmos multiplying dacs application note, publication number e630c-5-3/86 available from analog devices. analog-digital conversion handbookavailable from analog devices.
ad7541a C7C rev. b 20-terminal ceramic leadless chip carrier (e-20a) 1 20 4 9 8 13 19 bottom view 14 3 18 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) bsc 0 . 200 (5 . 08) bsc 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 18-lead plastic dip (n-18) 18 19 10 0.925 ( 23.49 ) 0.845 (21.47) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) outline dimensions dimensions shown in inches and (mm). 20-lead plastic leadless chip carrier (p-20a) 3 pin 1 identifier 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.02) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 18-lead cerdip (q-18) 18 1 9 10 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.960 (24.38) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 18-lead soic (r-18) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 18 10 9 1 0.4625 (11.75) 0.4469 (11.35) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1
C8C c718bC1C6/97 printed in u.s.a.
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